MCP Examples

• During cycles 16-12 the CPU does nothing, since reset is triggered.
• During cycles 11-9 the CPU starts running internally.
• During cycles 8-6 stack access is happening, because reset is implemented similar to an interrupt. The behavour until here might differ from chip to chip!
• During cycles 5-4 the reset vector is read, low byte first.
• During cycles 3-2 a NOP OpCode are processed. Since the OpCode takes two cycles to execute, the CPU triggers a dummy read on the following address. Just in case, there is a parameter for an instruction to fetch.
• During cycles 1-0 the next NOP OpCode is processed.

• During cycles 5-4 the reset vector is read, low byte first.
• During cycles 3-0 undocumented OpCodes are processed. This is handles differently on each variant:
  • (6502: the CPU executes two different instructions at once: ROL and AND.)
  • (65816: since each OpCode is defined, there is no example on how undefined OpCodes work.)
  • 65C02 and 65SC02: each undocumented OpCode is executing a "NOP", but the parameter can differ from OpCode to OpCode. This is a very interresting one: no dummy reads are executed, this instruction only requires a single clock cycle. This is not possible on the 6502 or 65816.
  • (65CE02 will execute a long range BMI; however, the NOP only takes a single cycle there)

The rest of the output show that the program running is in an endless loop once calculation is done. The output is of course the start of the Fibonacci sequence as far as it can be calculated in 8 bits. The code is stopping when the add overflows.

Source code: (excluding first JMP instruction)

   clc
   cld
   ldx   #$01
   stx   BUFFER+1
   dex
   stx   BUFFER

@loop:
   lda   BUFFER,x
   inx
   adc   BUFFER,x
   bcs   *
   inx
   sta   BUFFER,x
   dex
   bne   @loop

• After the reset, the first instruction is a JuMP, so I can easily modify the code without the need to change the start address.
• During the cycles 18-13 the CPU executes a Jump to SubRoutine:
  • 18: fetch the JSR OpCode
  • 17: fetch low byte of jump target address
  • 16: dummy read of stack
  • 15: write high byte of return address minus 1 to stack
  • 14: write low byte of return address minus 1 to stack
  • 13: fetch high byte of jump target address and perform jump
• The ReTurn from Subroutine starts at cycle 8 (cycle 9 is the dummy read from the NOP OpCode at 10):
  • 8: fetch the RTS OpCode
  • 7: dummy read non-existant parameter
  • 6: dummy read from stack
  • 5: fetch low byte of return address minus 1 from stack
  • 4: fetch high byte of return address minus 1 from stack
  • 3: dummy read from memory to adjust program counter to correct return address and jump back
  • 2-0: endless loop
• Interesting how the return address minus one gets written to stack and how it is compensated by the return call. This seems to be caused by the split of reading the low and high bytes of the target address.

Source code: (excluding first JMP instruction)

   jsr   jsrtest
   jmp   *

jsrtest:
   nop
   nop
   rts
   brk

• After the reset, the first instruction is a JuMP, so I can easily modify the code without the need to change the start address.
• Next the accumulator is loaded with a recognizable value ($42).
• Push the value on the stack
  • 11: fetch the PHA OpCode
  • 10: dummy argument read
  • 9: push value to the stack
• Pull the value from the stack
  • 8: fetch the PLA OpCode
  • 7: dummy argument read
  • 6: dummy read from stack to adjust stack pointer
  • 5: pull value from the stack
• End program
  • 4-0: endless loop

Source code: (excluding first JMP instruction)

   lda   #$42
   pha
   pla
   jmp   *

• after the reset, the first instruction is a JuMP, so I can easily modify the code without the need to change the start address.
• after that the IRQ vector gets set up, until "IRQ 9" is entered.
• main program waits for interrupts
  • 35-30: processing OpCodes NOP, NOP, and CLI (CLear Interrupt disable)
  • 29-27: processing endless loop JuMP, and wait for interrupt to trigger
• interrupt is triggered
  • 26-25: two dummy reads: interrupt is triggered while fetching OpCode
  • 24-23: write high byte and low byte of return address to the stack
  • 22: write processor status to stack
  • 21-20: read interrupt vector
  • 19-9: write to and read from stack (like previous example)
• returning from interrupts
  • 8: fetch RTI (ReTurn from Interrupt) OpCode
  • 7: dummy argument read
  • 6: dummy to adjust stack pointer
  • 5: read processor status from stack
  • 4-3: read low byte and high byte of return address from stack
• returned to main program
  • 2-0: process endless loop interrupt at 28-26
• it is noteworthy, that return address is not "minus one" as in the JSR

Source code: (excluding first JMP instruction)

   lda   #<irqtest
   sta   $fffe
   lda   #>irqtest
   sta   $ffff
   nop
   nop
   nop
   cli
   jmp   *

irqtest:
   pha
   nop
   nop
   pla
   rti
   brk

• after the reset, the first instruction is a JuMP, so I can easily modify the code without the need to change the start address
• After that the IRQ vector gets set up, and the BRK OpCode is processed
  • 37-26: set up IRQ vector which is also used for the software interrupt using BRK (BReaK)
  • 25: process BRK Opcode
  • 24: dummy argument read
• process BRK interrupt
  • 23-22: write high byte and low byte of return address to the stack   NOTE: the return address is the one after the dummy read, the documentation states that the BRK OpCode uses two bytes
  • 21: write processor status to stack
  • 20-19: read interrupt vector
  • 18-8: write to and read from stack (like previous example)
• return from interrupt
  • 7: fetch RTI (ReTurn from Interrupt) OpCode
  • 6: dummy argument read
  • 5: dummy to adjust stack pointer
  • 4: read processor status from stack
  • 3-2: read low byte and high byte of return address from stack
• returned from interrupt
  • 1-0: process the following NOP OpCode

Source code: (excluding first JMP instruction)

   lda   #<irqtest
   sta   $fffe
   lda   #>irqtest
   sta   $ffff
   brk
   nop
   nop
   nop
   jmp   *

irqtest:
   pha
   nop
   nop
   pla
   rti
   brk